Digital Verification Engineer for High-Speed Designs
22 hours ago
We are seeking a highly motivated and innovative Firmware Validation Engineer to join our team at Synopsys, Inc. This is an exciting opportunity to work on high-speed digital verification designs, collaborating with a team of experienced engineers.
Key Responsibilities:- Create and update test plans and test cases for high-speed digital and mixed-signal designs
- Develop modular constrained-random/coverage-driven Verilog, SystemVerilog, and UVM/VMM testbenches
- Write SystemVerilog assertions to ensure reliability and performance
- Maintain simulation regressions and debug RTL and gate-level simulation failures
- Conduct functional coverage and perform functional/code/assertion coverage analysis
- Track issues in Jira and document in Confluence
- Enhance the verification process for high-speed digital and mixed-signal designs
- Contribute to the successful development and delivery of high-end mixed-signal designs
- Ensure the reliability and performance of current and next-generation products
- Improve the efficiency of the verification process through innovative test plans and methodologies
- Collaborate with an expert team to achieve project milestones and deliverables
- Support the continuous improvement of verification strategies and tools
- Solid understanding of digital circuit design principles
- Basic understanding of C/C++ and RISC processors
- Hands-on experience in writing test cases in Verilog and SystemVerilog
- Familiarity with scripting languages (Python or Perl) and working in a Linux environment
- Knowledge of high-speed digital and mixed-signal design methodologies
A competitive salary of $120,000 per year, plus benefits and opportunities for professional growth.
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