Senior ASIC Design Verification Engineer
7 days ago
We are seeking a highly skilled and motivated ASIC Design Verification Engineer to join our team at US Tech Solutions.
About the Role:
The successful candidate will be responsible for managing and enhancing verification environments and regression workflows, as well as triaging and debugging regression results. Additionally, they will analyze test plan coverage, write, modify, and maintain test cases and libraries in SystemVerilog/UVM/Ruby.
Responsibilities:
- Maintaining and enhancing verification environment and regression workflow
- Triage and debug regression results
- Analyze test plan coverage
- Write, modify, and maintain test cases and libraries in SystemVerilog/UVM/Ruby
Requirements:
To succeed in this role, you will need:
- A minimum of 5 years of experience in Verification
- Experience with SystemVerilog, Verilog, and C/C++
- Strong understanding of UVM-based verification methodology
- Experience with Low Power Verification and debug methodology (desired)
- VCS/DVE familiarity is necessary
- Ability to juggle multiple on-going tasks at a time
- Strong, independent working ability
- Strong teamwork and communication skills
- Good attention to detail and creative thinking ability
About Us:
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. We offer competitive salaries, comprehensive benefits, and opportunities for growth and development.
Estimated Salary Range: $120,000 - $180,000 per year based on location and experience.
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