High-Speed Design Verification Expert
1 week ago
We are seeking a highly skilled Staff Design Engineer to join our team at Synopsys, Inc. in the United States.
Company OverviewAt Synopsys, we're at the heart of the innovations that change the way we work and play. We power the Era of Smart Everything with the world's most advanced technologies for chip design and software security.
Key Responsibilities:- Define and track Verification test plans
- Design and write constrained-random SystemVerilog testbenches using UVM
- Write SystemVerilog assertions
- Write functional coverage
- Debug RTL and GLS failures
- Perform code coverage analysis
- Provide mentoring and guidance to less experienced team members
- Bachelor of Science in Electrical Engineering (BSEE) or equivalent with 8+ years of industry experience
- Digital verification expertise in UVM environment; formal verification is a plus
- Understanding of DDR memory and DDRPHY architecture
- Knowledge of DFI, Memory Controller, or Memory Subsystem
- Proficiency in Verilog, SystemVerilog, and scripting languages like Perl/Python
- Strong debugging skills
- Demonstrated good communication and problem-solving skills
- Understanding of high-speed interface protocols is a plus
The estimated salary range for this position in the United States is between $180,000 and $250,000 per year, based on factors such as location, experience, and qualifications.
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