Senior Analog Design Engineer, High-Speed PLL Specialist

3 days ago

Markham, Ontario, Canada Synopsys, Inc. Full time

As a Senior Analog Design Engineer at Synopsys, Inc., you will play a crucial role in the development of high-speed PLL designs for next-generation datacenters, automobiles, and communications networks.

About the Role:

  • You will design and develop circuit-level PLL architectures, including VCOs, charge pumps, and voltage regulators, to support high-speed SerDes applications up to 112Gbps, 128Gbps, 224Gbps, and beyond.
  • Collaborate with cross-functional teams to integrate PLL designs into system-level platforms, leveraging FINFET and gate all around CMOS technologies.
  • Mentor junior designers and provide technical leadership to ensure the delivery of high-quality analog and mixed-signal circuits.
  • Interface with CAD teams to coordinate layout implementation and verification of custom circuits.

Requirements:

  • 8+ years of experience in CMOS analog and mixed-signal circuit design, with a Master's degree or PhD. Alternatively, candidates with a Bachelor's degree and additional experience may be considered.
  • Detailed knowledge of PLL loop operation and design principles.
  • Proven expertise in designing SerDes blocks and/or PLL circuit components, such as VCOs, charge-pumps, regulators, and high-speed dividers.
  • Familiarity with FINFET and gate all around CMOS technologies.
  • Proficiency in Hspice, Finesim, PrimeSim, or similar spice-type simulators.
  • Schematic entry skills using Synopsys Custom Designer or similar tools.
  • Awareness of digital timing analysis in PrimeTime and/or Nanotime is an asset.

What We Offer:

  • A competitive salary range: $180,000 - $220,000 per annum, based on location and experience.
  • A comprehensive benefits package, including medical, dental, and vision coverage, 401(k) matching, and paid time off.

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