Digital Design Engineer
1 day ago
We're seeking a highly skilled ASIC Digital Design Engineer to join our High Bandwidth Memory PHY RTL team at Synopsys, Inc.
Key Responsibilities- Design and develop RTL for High Bandwidth Memory PHY IP
- Collaborate with cross-functional teams to deliver high-quality designs
- Develop and maintain technical documentation
- Stay up-to-date with industry trends and emerging technologies
- 5-10 years of experience in RTL design, including interfacing with Mixed Signal Designs
- Strong understanding of high-speed circuit design and timing closure
- Proficiency in SystemVerilog and Verilog
- Ability to automate repetitive tasks using scripting languages
At Synopsys, we're committed to providing a collaborative and inclusive work environment. As a member of our team, you'll have the opportunity to work with talented individuals from diverse backgrounds and contribute to cutting-edge projects.
We're an equal opportunities employer and welcome applications from qualified candidates who share our passion for innovation and excellence.
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