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Senior ASIC Digital Design Engineer

2 months ago

Toronto, Ontario, Canada Synopsys, Inc. Full time
About the Role

We are seeking a highly skilled ASIC Digital Design Engineer to join our High Bandwidth Memory PHY RTL team at Synopsys, Inc. As a key member of our team, you will be responsible for designing and developing high-speed digital circuits, working closely with mixed signal and analog designers to deliver cutting-edge technology solutions.

Key Responsibilities
  • Design and develop high-speed digital circuits using SystemVerilog and Verilog
  • Collaborate with mixed signal and analog designers to ensure seamless integration of digital and analog components
  • Develop and deliver RTL designs that meet industry standards and specifications
  • Provide technical support to various teams and stakeholders
  • Stay up-to-date with the latest industry trends and technologies
Requirements
  • 5-10 years of experience in RTL design, including interfacing with mixed signal designs
  • Strong understanding of high-speed circuit design and timing closure
  • Excellent problem-solving skills and clear communication
  • Experience with scripting languages and automation tools
  • Knowledge of DFT/DFM flows and debugging complex hardware issues
Preferred Qualifications
  • Experience with DDR and HBM DRAM technologies
  • Ability to model analog and mixed signal circuits
  • Experience with physically aware synthesis and debugging
About Synopsys, Inc.

Synopsys, Inc. is a leading provider of electronic design automation (EDA) software and services. We are committed to innovation and excellence, and we are seeking talented individuals to join our team.