Senior ASIC Digital Design Engineer for High-Performance DDR PHY IP Development
4 weeks ago
Synopsys, Inc. is at the forefront of silicon design innovation, providing essential tools and intellectual properties to enable semiconductor development, verification, and production.
We are a leading provider of DDR PHY IP products, developing cutting-edge technologies for high-performance, high-bandwidth, low-latency, and low-power solutions.
This role offers an exciting opportunity to innovate and develop world-class market-leading DesignWare DDR PHY IP technology as a Senior ASIC Digital Design Engineer.
Job Overview- You will contribute to the development of DDR PHY IP solutions, shaping the next generation of product innovation, performance, and efficiency.
- This position requires expertise in synthesizable Verilog and System Verilog design concepts and implementation.
- The successful candidate will have experience with front-end design flows, including linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques.
- BS/MS in Electrical Engineering with at least 2 years of experience in complex technical development.
- A strong understanding of DDR memory and DDRPHY architecture is highly desirable.
- Excellent communication skills and self-motivation are essential for this role.
$120,000 - $160,000 per year
This salary estimate is based on industry standards and takes into account factors such as location, experience, and qualifications.
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