Staff ASIC Design Engineer
1 day ago
At BTA Design Services, we're seeking a Staff ASIC Design Engineer to join our team.
We value our people and foster an environment where everyone is appreciated, trusted, and engaged.
The ideal individual will have a strong background in complex RTL logic design, synthesis, and timing closure.
Key responsibilities include:
- Developing synthesis and timing constraints for complex logic blocks and sub-systems
- Designing and implementing complex RTL logic in Verilog or System Verilog
- Interface with the verification team, design team, hardware team, and support team
- Performing lab bring-up, product integration, and support
- Providing technical support to customers and leading them through complex technical issues
Requirements include:
- Minimum of an undergraduate degree in EE or equivalent skills/experience
- Minimum of 15+ years of relevant experience in progressive roles
- Experience with modern day ASIC development, including complex RTL logic design, synthesis, STA, lint, LEC, and understanding of PnR
- Deep experience developing synthesis and timing constraints for complex logic blocks and sub-systems
- Experience with complex asynchronous clock boundaries and high-speed serial interfaces
- Experience in a lab environment, troubleshooting issues up to the system level
- Experience or knowledge in one or more of the following required: ARM A** Application Processor Sub-Systems, Processor Fabric Interfaces, Caches, Non-Volatile memory, Networking Switch/Router Datapaths, Packet Processing, OTN, Ethernet
- Experience with industry standard interfaces, e.g. 10/25/40/100Gb Ethernet and OTN, PCIe, SPI, I2C, USB, AXI, AHB, AMBA, GPIO, SRIO, DDR/SDRAM/DMA, NV Memories
- Test verification and scripting experience is a must
- Track record as a self-starter, a team player, and a leader
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