Digital Verification Engineer Intern for High-Performance Designs

5 days ago


Markham, Ontario, Canada Synopsys Full time
Overview:
We drive the innovations that shape our world. At Synopsys, we lead in chip design, verification, and IP integration. Our technology is central to the Era of Pervasive Intelligence, empowering the creation of high-performance silicon chips and software content.

Salary:
$90,000 - $120,000 per year

About You:
As a highly motivated and innovative individual with a passion for digital and firmware verification, you thrive in dynamic environments. With hands-on experience in writing test cases in Verilog and System Verilog, you have a basic understanding of assembly language programming and RISC processors. Familiarity with scripting languages (Python or Perl) and working in a Linux environment makes you a great fit for our team. You are organized, communicate effectively, and are ready to contribute to a highly experienced mixed-signal design team.

Job Responsibilities:
You will be responsible for:
  • Writing modular constrained-random Verilog, System Verilog testbenches and UVM/VMM testbenches
  • Executing system-level tests and validation in a prototype environment
  • Performing functional coverage, assertion coverage, and code coverage
  • Tracking issues in Jira and documenting in Confluence
  • Creating and updating test plans and test cases
  • Monitoring simulation regressions and analyzing failure cases

The Impact You Will Have:
Ensure the reliability and functionality of high-performance digital and mixed-signal designs. Contribute to the development of next-generation Backplane Ethernet, PCIe, SATA, and USB SERDES products. Improve the efficiency of our verification processes through innovative testbench designs. Collaborate with cross-functional teams to resolve complex verification challenges. Enhance product quality by identifying and addressing potential issues early in the design cycle. Support the continuous improvement of our verification methodologies and tools.

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