Senior RTL Design Engineer

3 weeks ago

Vancouver, British Columbia, Canada Advanced Micro Devices inc. Full time
Transform Lives with AMD Technology

We're passionate about pushing the limits of innovation to solve the world's most important challenges. As a Senior RTL Design Engineer at AMD, you'll be part of a cutting-edge team that delivers industry-leading Memory IP and helps our experts develop leading-edge Memory interfaces.

The Role

Join our Memory IO team in developing high-speed LPDDRx, DDRx, and associated ownership and development of DDR Subsystems. You'll be responsible for defining product features and capabilities, close architecture, and micro-architecture requirements, and providing technical direction to execution teams.

Key Responsibilities
  • Define product features and capabilities, close architecture, and micro-architecture requirements
  • Drive technical specifications for SoC and IP blocks to meet those requirements
  • Provide technical direction to execution teams
  • Work cross-functionally with IP/Domain architects to identify and assess complex technical issues/risks
  • Develop architectural solutions to achieve product requirements
  • Knowledge sharing and other contributions to Platform & System Architecture
  • Responsible for architecture analysis and technical solutions for marketing/feature change requests
  • Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution, and Performance/Power Verification sign-offs
Requirements
  • Excellent knowledge of System Verilog and Verilog language with respect to RTL design
  • Advanced DDR subsystem architecture, microarchitecture, development, and implementation experience
  • Excellent debug skills and knowledge of key DDR subsystem components
  • Development and maintenance of DDR Subsystem integration, documentation, timing, and floor planning through the lifecycle of pre-silicon development
  • Subsystem and block-level documentation as well as timing diagrams
  • In-depth knowledge of standard IP interfaces, communication of interfaces, and IP interface protocol and utilization
  • Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware-level clocking and multi-domain simulation synchronization
  • Clock domain crossing implementation experience
Preferred Experience
  • Outstanding foundation in Systems & SoC architecture, with expertise in Memory sub-system, Fabrics, CI/O subsystems, Clocks, Resets, and Security
  • Experience analyzing System-level Micro-Architectural features to identify performance bottlenecks within different workloads
  • Demonstrated expertise in power management microarchitecture, low power design, and power optimization, along with power impact at architecture, logic design, and circuit levels
  • Experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controller RTL design and development
  • Knowledge and experience developing SVA/OVL and synthesizable assertions
  • Experience stitching block-level IP together to form subsystems
  • VCS and Zebu Emulation verification and debug experience
  • Strong knowledge of git and perforce
  • UPF experience and knowledge of power supply implementations across subsystems and writing logic and timing constraints to handle clock domain crossings
Academic Credentials

Bachelor's degree in Electrical or Computer Engineering and relevant experience, or Master's or PhD degree in Electrical or Computer Engineering with relevant experience.

Location: Vancouver, BC or Markham, ON

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