A&ms Layout Design Engr, Ii

5 months ago

Markham, Canada Synopsys Full time

48585BR
- CANADA - Ontario - Markham, CANADA - Ontario - Mississauga

**Job Description and Requirements**

Job Description and Requirements

As an A&MS Layout Engineer, II, you will collaborate in the development of advanced analog integrated circuit designs using best-in-class Synopsys suite of tools. You will be working with local and global SERDES teams in developing layout for complex analog mixed-signal designs in the latest technology nodes. In your role you will be responsible for taking on low-to-medium-level block ownership and the creation of complex blocks. As a member of our Solutions IP Design Group, you will be developing IP in various technology nodes and foundries for various customers in a fast paced environment.

**Responsibilities and Duties**
- Leading and managing top-level blocks
- Coordinating with other layout team members for top-level integration as well as designing and reviewing layout designs
- Collaborate with circuit team for feasibility layout of new products
- Optimize layout designs for performance, power, and area
- Work with RnD Experts to perform layout verification and resolve any design-related customer issues

**Qualifications**
- BSEE or MSEE with at least 2 years of direct industry experience
- Knowledge or understanding with regards to the layout of analog and mixed signal CMOS circuits
- Experience with full custom analog layout design tool: Custom Compiler (or equivalent) is a plus
- Experience with advanced FinFET nodes is a plus
- Ability to use foundry design rule manuals to debug DRC errors is required
- Good written and verbal English skills
- Experience with TCL, SKILL, PERL, Python or other language scripting is a plus
- Experience or knowledge with regards to:

- Layout design with consideration for reliability (EMIR/DFM)
- Layout design to optimize for parasitic layout effects (matching/proximity effects)
- Layout optimization for signal integrity (clock/data routes, differential routing, shielding)
- Experience with ESD design constraints, latch-up risk mitigation is a plus
- Experience with PERC is a plus
- Has excellent communication skills, ability to interact with cross-functional teams
- Experience with the following tools is a plus:

- Jira/Atlassian
- ICV Work Bench
- ICC/ICC2/Fusion Compiler

LI-DP1
- **At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.**

**Job Category**
- Engineering

**Country**
- Canada

**Job Subcategory**
- Layout Design

**Hire Type**
- Employee

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