Senior Asic Design Engineer – Rtl, Synthesis
2 days ago
toronto, canada
Btadesignservices
Full-time
Free with email or Google
Save this job and keep your search organized
Create a free account to save jobs, create alerts and return to this listing from your dashboard.
Free with email or Google
By continuing, you agree to our Terms & Privacy Policy.
Seeking a Senior ASIC Design Engineer for AI/HPC SOCs, involving system to spec translation and synthesis constraint development. Requires 8+ years of ASIC design experience, Verilog/System Verilog proficiency, and lab troubleshooting skills.