Verification Engineering Lead
2 days ago
About the Role
At Synopsys, Inc., we are seeking an experienced Verification Engineer to lead our design verification efforts.
Key Responsibilities
- Evaluate and optimize verification plans for chip/module level designs using System Verilog with UVM.
- Apply advanced verification techniques such as constrained random generation, functional coverage, assertions, and formal verification.
- Develop and implement test cases, checkers, and coverage that align with the verification test plan.
Requirements
- Bachelor's or Master's degree in a relevant field with significant digital verification experience in the industry.
- Proven expertise in verifying interfaces and controllers for high-speed serial protocols like PCI-Express, CXL, or SAS/SATA.
- Experience with RTL verification using coverage-driven techniques.
- Familiarity with scripting languages and programming experience in C, C++.
- Proficiency in HDL languages including System Verilog, Verilog, or VHDL.
- Excellent analytical, oral, and written communication skills.
- A self-motivated team player who can adapt to new challenges.
What We Offer
- A competitive salary of approximately $120,000 per year, reflecting your exceptional qualifications and industry standards.
- The opportunity to grow and manage end-to-end verification processes.
- A customer-facing role working closely with pre-sales and post-sales teams.
- Autonomy to develop systematic solutions for emerging problems and contribute to product architectures, quality, and development strategies.
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