Architect of Advanced I/O Connectivity Solutions
3 weeks ago
The AMD IOHUB Team is seeking a skilled ASIC Design Verification Engineer to contribute to the development of leading-edge I/O connectivity and virtualization technologies. As a key member of the team, you will be involved in all aspects of IP verification, from creating verification architectures to defining test plans and developing verification environments.
Key Responsibilities:
- Collaborate with IP architects to design and develop verification architectures
- Participate in the verification of complex IP blocks and take ownership of key features
- Work on test plans, verification environment development, and regression
- Develop and maintain VIP, libraries, verification environments, and testcases using System Verilog/UVM/SystemC
- Triaging and debugging regressions, analyzing code and functional coverage, and deploying industry-leading verification methodologies
Requirements:
- Strong ASIC verification experience and understanding of digital design and computer architecture
- Proficient in Verilog, System Verilog, C/C++, UVM, OOP, and working in Linux and Windows environments
- BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science
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