Digital Verification Engineer-Lead Role
1 month ago
Job Title: Staff Digital Verification Engineer-Lead Role
Job Summary:
We are seeking a highly skilled Staff Digital Verification Engineer to lead our verification team and contribute to the development of industry-leading mixed-signal Application Specific Integrated Circuits. The ideal candidate will have a strong background in SystemVerilog UVM and ASIC verification, with experience in functional coverage driven verification sign-off and contributing to verification plans.
Key Responsibilities:
- Lead the verification of mixed-signal ASICs in a SV UVM environment.
- Implement test cases based on functional specifications and test plans.
- Debug mixed-signal chips in digital simulation.
- Implement functional coverage and aid designers in reviewing code coverage.
- Mentor less experienced engineers.
Requirements:
- Bachelor's degree or equivalent technical degree in Electrical/Computer/Software Engineering.
- 8+ years of practical design verification experience using SystemVerilog UVM and ASIC verification.
- Experience with functional coverage driven verification sign-off.
- Experience contributing to verification plans.
Preferred Skills:
- Knowledge of PLLs.
- Experience with Synopsys and/or Cadence simulation tools.
- Ability to work in a Unix/Linux operating system environment.
- Knowledge of scripting languages such as Python or equivalent.
- Experience with mixed-signal design modelling and debugging.
About Us:
We are a leading company in the energy industry, and we are committed to providing our employees with a challenging and rewarding work environment. If you are a motivated and experienced verification engineer looking for a new challenge, please submit your application.
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