Design Verification Expert
1 week ago
We are seeking a skilled Design Verification Engineer to join our team at undisclosed. As a seasoned professional, you will be responsible for ensuring the highest quality in digital systems.
Key Responsibilities:
- Develop robust verification plans and environments for chip/module level designs using System Verilog with UVM.
- Apply advanced verification techniques such as constrained random generation, functional coverage, assertions, and formal verification.
- Collaborate with design and architecture teams to understand design specifications and derive verification requirements.
- Analyze and debug test failures to identify issues and drive them to resolution.
Requirements:
- Bachelor's or Master's degree with relevant digital verification experience in the industry.
- Experience in verification of interfaces and controllers for high-speed serial protocols such as PCI-Express, CXL, or SAS/SATA.
- Proficiency in RTL verification using coverage-driven verification techniques.
- Expertise in HDL languages such as System Verilog, Verilog, or VHDL.
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