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Signal Verification Engineer

2 months ago


Mississauga, Ontario, Canada Synopsys Full time

At Synopsys, we're driving technology innovations that shape the way we live and connect. Our Era of Pervasive Intelligence is fueled by smart tech and AI, seamlessly woven into daily life. From self-driving cars to renewable energy systems, our high-performance silicon chips efficiently distribute clean power, creating a healthier, safer, and more sustainable world.

Internship Experience

As a Mixed Signal Design Verification Intern, you'll dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide. You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path.

Mission Statement

We fuel today's innovations and spark tomorrow's creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive - both at work and beyond.

Key Responsibilities
  • Setup UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs in both analog and digital coexist environments
  • Analyze / verify the functionalities of SERDES
  • Define and track verification test plans
  • Debug simulation failures in both analog and digital domains
  • Create top level analog testbenches for SERDES
  • Perform physical layout reliability analysis for SERDES
Requirements
  • Currently pursuing a bachelor's degree in Electronic Engineering, Computer Science, or related field in the penultimate year of study
  • Strong knowledge of analog circuitry such as bandgap, opamp, PLL, Transmitter/Receiver designs etc.
  • Ability to write scripts in languages such as Perl, Python and Unix shell
  • Familiar with Verilog and SystemVerilog
Program Facts
  • Program Length: 12-16 months
  • Location: Mississauga, Canada
  • Working Model: Hybrid
  • Full-Time/Part-Time: Full-time

Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply. If you need assistance or a reasonable accommodation during the application process, please reach out to us. Estimated salary: $60,000 - $80,000 per annum.