Digital Verification Engineer Internship
3 weeks ago
Synopsys is seeking a highly motivated engineering student to join our Solutions Group in Mississauga as an intern for a 16-month period starting in May 2025.
The candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, USB 3/4, and/or MIPI CPHY/DPHY SERDES products.
This is an excellent opportunity to work with digital and mixed signal design engineers accountable for delivering high-end mixed-signal designs.
The position offers a chance to learn and develop skills in defining and tracking verification test plans, designing and writing constrained-random system verilog testbenches, and creating and examining functional coverage.
Key Responsibilities:
- Defining and tracking verification test plans
- Designing and writing constrained-random system verilog testbenches using a verification methodology such as UVM
- Creating and examining functional coverage
- Writing system verilog assertions
- Debugging RTL and gate level simulation failures
- Firmware debugging
- Bug tracking using software tools such as Jira
- Code coverage analysis
Requirements:
- Experience writing scripts in languages such as Perl, Unix shell, or Python
- Experience with any object-oriented programming language (C++, Java, Python, etc.)
- Familiar with verilog or system verilog
At Synopsys, we value the diversity of our workforce and are committed to providing access and opportunity to individuals with disabilities. We offer a dynamic and inclusive work environment and provide reasonable accommodations to applicants throughout the recruitment and employment process. Please contact hr-help for assistance.
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