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Senior ASIC Validation Engineer
3 months ago
Infinera stands as a prominent provider of cutting-edge networking solutions on a global scale.
Our clientele encompasses leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government entities worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs.
We specialize in the design, development, and delivery of hardware and software solutions for fiber-based connectivity that covers access, aggregation, metro, long haul, and submarine networks.
Our pioneering edge-to-core solutions serve as the backbone for many of the world’s largest and most demanding networks, generating substantial service revenue for our clients.
Position Summary:
As a Senior ASIC Validation Engineer, you will be responsible for the development of System Verilog/UVM based protocol and traffic generators/checkers, alongside the formulation of test plans derived from functional requirements and relevant standards.
Key Responsibilities:
1. Design and implement test plans at the block or sub-chip levels for intricate ASICs.
2. Exhibit proficiency in System Verilog and scripting languages, particularly Python.
3. Define, develop, and execute self-checking tests for complex digital ASICs.
Qualifications:
- A Master’s degree is preferred; a Bachelor’s degree in Computer Science or Electrical Engineering is mandatory.
- A minimum of 3 years of pertinent experience in the ASIC verification domain is required.
Equal Opportunity:
All qualified candidates will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera adheres to all applicable state and local laws governing nondiscrimination in employment.
