Senior ASIC Verification Engineer
2 weeks ago
Job Summary
We are seeking a highly skilled Senior ASIC Verification Engineer to join our team at Infinera. The ideal candidate will have a strong background in digital ASIC verification and experience with System Verilog and UVM methodology.
Key Responsibilities
- Contribute significantly to the development of verification infrastructure
- Develop System Verilog/UVM-based protocol/traffic generators/checkers and test plans based on functional requirements and applicable standards
- Work on developing and implementing test plans at the block or sub-chip levels for complex ASICs
Requirements
- Masters degree desired, Bachelor's degree in CS/EE required
- 8+ years of relevant experience in ASIC verification
- Fluent in System Verilog and scripting languages such as Python
- Intimate knowledge of UVM methodology
- Knowledgeable about assertions and functional coverage
- Experience with code coverage and formal verification tools
- Very good communication skills and ability to work in a geographically diverse team environment
Preferred Qualifications
- Knowledge of DSP and/or FEC
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