Senior Staff Design Verification Engineer

4 weeks ago

Toronto, Ontario, Canada Lightmatter Full time

Senior Staff Design Verification Engineer

At Lightmatter, we are at the forefront of developing chips that facilitate extreme-scale artificial intelligence computing clusters. We seek a dedicated engineer or scientist who thrives on collaboration, innovation, and tackling complex technical challenges while contributing to groundbreaking projects like the world's first optical computers.

As a Senior Staff Design Verification Engineer, you will play a pivotal role within a vibrant, interdisciplinary team. Your work will involve close cooperation with our digital design specialists, employing UVM testbench methodologies to meticulously validate their designs. You will engage with photonic and analog designers, gaining in-depth insights into their innovative approaches and applying Real Number Modeling (RNM) along with AMS verification techniques. This essential function is critical to maintaining the integrity of our designs.

Your collaboration with the Architecture team will be vital for understanding system requirements and leading performance verification efforts. This position provides a unique opportunity to advance your expertise across various domains, including UVM, AMS modeling, mixed-signal verification, formal verification, emulation, and both performance modeling and verification.

Key Responsibilities
  • Collaborate with teams focused on digital, photonics, and analog design to create thorough test plans.
  • Design and execute UVM testbenches for both subsystem-level and full-chip verification, including debugging testbenches, resolving issues, achieving high coverage, and overseeing the final sign-off on Design Verification (DV).
  • Develop Real Number Models (RNM) for photonic and analog circuits, conduct AMS verification alongside UVM, and ensure accurate model representation. Significantly contribute to the development of the Golden Reference Model (GRM) for design verification, and play an integral role in executing emulation and formal verification for DV purposes.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
  • A minimum of 12 years of experience in design verification and SystemVerilog.
  • At least 2 years of experience with Python.
  • Proficiency in developing the UVM library.
  • Familiarity with simulators such as Xcelium, ModelSim, Questa, or VCS.

Preferred Qualifications

  • Master's degree or higher in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
  • Experience with AMS verification.
  • Experience in formal verification.
  • Strong problem-solving skills, effective communication, and teamwork abilities.
  • Subject matter expertise in the technical areas outlined in the requirements.
  • Previous leadership experience.
  • Ability to communicate complex concepts effectively to diverse stakeholders, fostering support and consensus for initiatives.

Benefits

  • Comprehensive Health Care Plan.
  • Group Retirement Savings Plan matching.
  • Life Insurance.
  • Generous Time Off (Vacation, Sick & Public Holidays).
  • Training & Development opportunities.
  • Flexible, hybrid workplace model.
  • Stock Option Plan.

Lightmatter is committed to fostering a diverse and inclusive workplace, ensuring equal opportunity in recruitment, employment, training, compensation, and promotion without regard to race, religion, color, national origin, sex, disability, age, veteran status, or any other protected status as required by applicable law.

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