Principal Engineer

3 weeks ago

Burnaby, British Columbia, Canada Microchip Technology Full time
Job Description:

**About the Role:**

We are seeking a highly skilled Principal Engineer-Design to lead the development of complex digital integrated circuits at the block, subsystem, or device level. As a key member of our Data Center Solutions (DCS) Business Unit, you will be responsible for designing and implementing industry-leading performance, reliability, and security for PCIe Switches and NVME Controllers.

Key Responsibilities:

  • Design and develop complex digital integrated circuits using Verilog and System Verilog.
  • Define subsystem/block feature sets and describe design and implementation details in engineering documents and registers documents.
  • Support emulation, ASIC lab validation, including lab debug and providing logic modifications and workarounds.
  • Collaborate with cross-functional teams to resolve issues, communicate status, and solve technical problems.
  • Communicate with architects to justify design implementation decisions and associated trade-offs.
  • Stay up-to-date with applicable storage and computer interface protocol standards.

Requirements and Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent.
  • 8+ years of related experience.
  • RTL Design experience using System Verilog, Verilog is required.
  • Experience and understanding of complex ASIC design flows, including block and chip level simulation and debug, logic synthesis, static timing analysis, layout, and revision control.
  • Experience with Formal Verification is a plus.
  • Working knowledge of design and verification tools such as Synopsys Design Compiler, Cadence Incisive, waveform viewers, and other similar tools.
  • Scripting and programming skills using csh, bash, perl, python, tcl, etc.
  • Protocol knowledge and experience in PCI-Express is an asset.
  • Knowledge of AHB/AXI bus protocols is desired.
  • Excellent knowledge in logic synthesis and static timing analysis.
  • Experience in designing the chip top level with IOs, pin out, and package design.
  • Worked with physical design teams for layout implementation. Familiar with low power methodology and flows.
  • Capable of debugging EDA tool issues or design-related issues.
  • Working knowledge of DFT.
  • Excellent analytical and debugging skills and the ability to proactively solve issues.
  • Good verbal and written communication skills in English are an asset.
  • Excellent teamwork and time management skills, self-direction, the ability to work under pressure, and the desire to excel in a competitive environment.

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