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Principal Design Verification Engineer
2 months ago
Our DDR PHY IP team is Hiring a Principal Digital ASIC Verification Engineer.
In this role you will be responsible for developing test benches and verifying integrated IP Subsystems for our global customers. You will triage issues by working independently with architects and RTL designers while providing technical leadership on verification for initial specification to tape out.Exceptional Verilog, System Verilog, Perl/Python scripting, Makefile skills Solid Debugging skills and ability to root cause issues