Principal Digital Validation Engineer
3 weeks ago
Key responsibilities:
- Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …)
- Generate verification test plan, verification environment documentation and test environment usage documentation
- Define, develop, and verify complex UVM verification environments
- Evaluate and exercise various aspects of the development flow, which may include Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage)
- Collaborate with architect, designers, and VIP team to accomplish tasks
- Identify design problems, possible corrective actions, and/or inconsistencies in documented functionality
- Work with peers to improve methodologies and enhance execution efficiency
- Adhere to quality standards and good test and verification practices
- Work as a lead, mentor junior engineers, and assist them in debugging complex problems
- Support customer issues through reproduction and analysis
- Multitask between different activities
Key Qualifications:
- Proven desire to learn and explore new state-of-the-art technologies
- Demonstrate good written and spoken English communication skills
- Demonstrate good review and problem-solving skills
- Knowledgeable in Verilog, VHDL, and/or SystemVerilog
- Knowledgeable in scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus
- Understanding of verification methodology such as UVM
- Good organization and communication skills
- Be a solution provider
- 15+ years of relevant experience
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