Principal Digital Validation Engineer

3 weeks ago


Ottawa, Canada Synopsys, Inc. Full time

Key responsibilities:

  1. Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …)
  2. Generate verification test plan, verification environment documentation and test environment usage documentation
  3. Define, develop, and verify complex UVM verification environments
  4. Evaluate and exercise various aspects of the development flow, which may include Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage)
  5. Collaborate with architect, designers, and VIP team to accomplish tasks
  6. Identify design problems, possible corrective actions, and/or inconsistencies in documented functionality
  7. Work with peers to improve methodologies and enhance execution efficiency
  8. Adhere to quality standards and good test and verification practices
  9. Work as a lead, mentor junior engineers, and assist them in debugging complex problems
  10. Support customer issues through reproduction and analysis
  11. Multitask between different activities

Key Qualifications:

  1. Proven desire to learn and explore new state-of-the-art technologies
  2. Demonstrate good written and spoken English communication skills
  3. Demonstrate good review and problem-solving skills
  4. Knowledgeable in Verilog, VHDL, and/or SystemVerilog
  5. Knowledgeable in scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus
  6. Understanding of verification methodology such as UVM
  7. Good organization and communication skills
  8. Be a solution provider
  9. 15+ years of relevant experience
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