Design & Validation Engineer

2 months ago


Ottawa, Canada Synopsys, Inc. Full time
p>Experienced Design Verification Engineer

Responsibilities

  • Define verification plans and build verification environments for chip/module level designs using System Verilog with UVM.
  • Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification.
  • Write test cases, checkers, and coverage that implement the verification test plan.

Job Requirements

  • Bachelors or Masters with relevant digital verification experience in the industry
  • Experience of verification of interfaces and controllers for high-speed serial protocols such as PCI-Express, CXL, or SAS/SATA
  • RTL verification using coverage driven verification techniques
  • Scripting in any language. Programming experience or coursework in C, C++
  • Proficient in HDL languages System Verilog, Verilog, or VHDL
  • Good analytical, oral, and written communication skills
  • Self-motivated, proactive team player

Unique opportunities presented with this position

  • To grow and manage verification of product end-to-end.
  • Customer-facing role working in close collaboration with pre and post-sales team
  • Develop systematic ways to address new problems, think outside of the box
  • Have an impact on the new product architectures, quality and development strategies
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