Design Verification Engineer

3 weeks ago

Markham Ontario, York region, Canada LanceSoft, Inc. Full time

Location: Markham - on-site or hybrid (3 days a week in the office)


THE ROLE:

As a Design Verification Engineer, you will work with leading industry tools and design/verification concepts to assist in developing the design, verification and infrastructure components of a variety of digital design blocks. You will work closely with senior design and verification engineers to help develop a testplan for pre-silicon Digital Design Verification, assist in the development of a testbench to exercise the design, develop test-cases based on the testplan and coverpoints/assertions to achieve verification closure. You will also manage, and monitor regression runs for different blocks, report bugs/failures that occur, and actively debug the failures found.


A project usually has a year timeline and there are many products that the GFXIP is deployed into, including main-stream, mobile, workstation, machine-intelligence GPUs, APUs and gaming consoles.


THE PERSON:

The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or a logic design and verification issue. You should be able strike a balance between collaborative problem-solving and independent solution development.


KEY RESPONSIBILITIES:

• Design Verification of digital design blocks:

o Help create a test plan that outlines required verification work for project.

o Produce verification code that tests RTL design functionality using UVM (Digital design verification framework built using SystemVerilog) as per test plan.

o Write cover points to make sure verification items are properly exercised.

o Work on necessary debugging of verification code; fix tests to hit cover points if coverage is failing.

o Use Formal Verification techniques as needed.

• Manage and monitor regressions (regular repeated runs of same set of mostly random tests) for team’s blocks and fix errors in failing tests.

• Generate and analyze coverage reports to ensure exhaustive verification of the design and all possible end-cases.

• Write and edit csh, perl, python or ruby scripts to automate verification.

• Regular review and sign-off of design verifcation work at key project milestones.


REQUIREMENTS:

• Solid fundamental understanding of Computer Architecture and Digital Design concepts.

• Strong background in OOP coding techniques.

• Experience to Verilog or SystemVerilog; experience with UVM.

• Familiarity with scripting languages: perl or tcl or ruby or Bash or python, etc.

• Strong analytical skills and attention to detail.

• Excellent written and verbal communication skills.


GROWTH OPPORTUNITIES:

• Will get an understanding of how TLBs, data caches, data transfer protocols, data compression algorithms, threading, pipelining, timing analysis, and other computer architecture concepts are used in commercial ASIC design and verification.

• Opportunity to learn end to end Graphics Accelerator Pipeline and Graphics rendering concepts such as rasterization and ray tracing

• Will build expertise in Verilog, SystermVerilog, and OOP techniques used in complex design development.

• Universal Verification Methodology (UVM), and SystemVerilog Assertion Based Verifcation (ABV).

• Exposure to Formal Verification Techniques.

• Work with sophisticated industry standard tools such as Synosys VCS, Verdi, VC Formal, etc.

• Be directly involved in the development of next-generation computer products.

• Develop communication skills further in a professional environment; meet and connect with industry experts and professionals


ACADEMIC CREDENTIALS:

• Bachelor’s Degree in Computer, Electrical, Mechatronics Engineering or Engineering Science or similar


LOCATION: Markham, ON Canada

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