Senior Cosim Engineer
3 weeks ago
Responsibilities include:
- Setup UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs in both analog and digital coexist environment
- analyzing/verifying the functionalities of SERDES
- Defining and tracking verification test plans
- Debugging simulation failures in both analog and digital domains
- Creating top level analog testbenches for SERDES
- Performing physic layout reliability analysis for SERDES
Requirements:
- Ability to write scripts in languages such as Perl, Python and Unix shell.
- Familiar with Verilog and SystemVerilog.
- Experience or knowledge with analog circuitry such as bandgap, opamp, PLL, Transmitter/Receiver designs.
Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world’s broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
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