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Sr. Digital Design Verification Engineer
2 weeks ago
Design Verification Engineer
Responsibilities
- Define verification plans and build verification environments for chip/module level designs using System Verilog with UVM.
- Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification.
- Write test cases, checkers, and coverage that implement the verification test plan.
- Bachelors or Masters with relevant digital verification experience in the industry
- Experience of verification of interfaces and controllers for high-speed serial protocols such as PCI-Express, CXL, or SAS/SATA
- RTL verification using coverage driven verification techniques
- Scripting in any language. Programming experience or coursework in C, C++
- Proficient in HDL languages System Verilog, Verilog, or VHDL
- Good analytical, oral, and written communication skills
- Self-motivated, proactive team player
- To grow and manage verification of product end-to-end.
- Cross-functional learning and interaction with professional teams across domains and geographies.
- Customer-facing role working in close collaboration with pre and post-sales team
- Develop systematic ways to address new problems, think outside of the box
- Have an impact on the new product architectures, quality and development strategies
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact #J-18808-Ljbffr
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