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Design Validation Engineer
3 months ago
Define verification plans and build verification environments for chip/module level designs using System Verilog with UVM.
Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification.
Write test cases, checkers, and coverage that implement the verification test plan.
Bachelors or Masters with relevant digital verification experience in the industry
RTL verification using coverage driven verification techniques
Scripting in any language. Programming experience or coursework in C, C++
Proficient in HDL languages System Verilog, Verilog, or VHDL
Have an impact on the new product architectures, quality and development strategies
At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Synopsys Canada ULC values the diversity of our workforce.
We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.
Should you require an accommodation, please contact hr-help-.