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Design Implementation Engineer
1 week ago
All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Senior Design Verification Engineer
Define verification plans and build verification environments for IP level designs using System Verilog with UVM.
Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification to achieve functional safety metrics (including ISO26262 compliance) for automotive applications
Write test cases, checkers, and coverage that implement the verification test plan.
Provide technical leadership to junior engineers and interns
Bachelors or Masters with 1+ years of digital verification experience in the industry
RTL verification using coverage driven verification techniques
Scripting in any language. Programming experience or coursework in C, C++
Proficient in HDL languages System Verilog, Verilog, or VHDL
Have an impact on the new product architectures, quality and development strategies
Synopsys Canada ULC values the diversity of our workforce.
We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.
Should you require an accommodation, please contact hr-help-.-
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