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Design Verification Engineer

3 months ago

Markham, Canada US Tech Solutions Full time
THE ROLE:
The Display Controller team is looking for an individual to participate in the design verification of the Display IP.

The Person:
The candidate would participate on a team of design verification, architects and design engineers, working closely with other team members to understand and verify the functionality of the design within the context of the unit, block, and overall system.

The candidate would be responsible for carefully documenting and executing test plans consisting of directed and random tests to be run under simulation.

The candidate would be expected to adopt evolving verification methodologies used in the industry as well as develop custom techniques to functionally verify increasingly complex IP designs within aggressive, market-driven schedules

KEY RESPONSIBILITIES: 
• Collaborate with architects and designers to understand the new features to be verified
• Understand the functional and performance requirements of the Display IP within an APU and dGPU SOC
• Assume technical leadership and hands-on development tasks
• Scope requirements and resources to meet demanding project schedules
• Create, reuse and debug test cases and test bench components for IP and SOC consumption
• Integration and codeline management
• Compose test and coverage plan to ensure functional completeness
• Signoff IP quality for delivery into SOC
• Effectively communicate with multi-disciplined teams located across the globe

 PREFERRED EXPERIENCE: 
• Proficient in IP level ASIC verification
• + years of proven verification experience on large ASIC development projects or equivalent embedded programming experience with a deep understanding of hardware architecture
• Experienced with Verilog, System Verilog, C, and C++
• Experience working with Synopsys VCS or equivalent
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributed compute environment.
• Exposure to simulation profile, efficiency improvement, acceleration, tools/process
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset
• Desirable assets with prior exposure to display IP or other multimedia solutions. 
• Strong analytical skills and attention to detail
• Excellent written and communication skills
• Team player with proven leadership skills

US Tech Solutions ( ) is global firm providing a wide-range of talent on-demand and total workforce solutions. We are an Equal Opportunity Employer and Prohibit Discrimination and Harassment of Any Kind.

Tech Solutions, Inc. is an Affirmative Action, Equal Opportunity Employer. Our employment decisions are made without regard to race, color, religion, gender, national origin, age, disability, marital status, veteran or military status, or any other legally protected status.