ASIC Digital Design, Architect

We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are You are a strategic thinker with a passion for designing robust verification processes. With deep expertise in ASIC development, mixed-signal verification, and high‑speed protocols like PCIe and Ethernet, you excel at architecting comprehensive test plans and collaborating with cross‑functional teams. You thrive in environments where your technical insights drive clarity and structure, and your communication skills help align project owners and stakeholders. You are comfortable working at the intersection of technology and team leadership, consistently seeking opportunities to innovate and improve. Your commitment to diversity and inclusion enhances your ability to build consensus and drive successful outcomes. What You’ll Be Doing Leading the design and creation of Unified Test Plans for HPC DSP‑based SERDES PHY products, ensuring all verification and validation phases are seamlessly integrated. Collaborating closely with project owners, product stakeholders, and cross‑functional teams to align verification strategies and resolve technical challenges. Architecting robust verification workflows leveraging UVM methodology and SystemVerilog, including VIP integration. Developing and refining automation scripts (Shell, Perl, Python, C++) and evaluating AI‑based approaches to support design and verification. Ensuring comprehensive coverage and traceability in test plans for high‑speed data recovery circuits. Facilitating knowledge sharing, effective communication, and organizational clarity across teams. The Impact You Will Have Shape the architecture and strategy behind flagship silicon IP product verification. Drive alignment and clarity among project teams, accelerating innovation and delivery. Influence global standards in data recovery and signal processing through robust test‑plan design. Empower teams to resolve technical challenges and reach milestones efficiently. Foster a collaborative, inclusive engineering culture. Support mentorship and professional development within a multidisciplinary team. What You’ll Need 10+ years of ASIC development and mixed‑signal verification experience. Expertise in PCIe, Ethernet protocols, and digital signal processing. Strong background in SystemVerilog and UVM methodology for environment architecture. Proficiency in scripting (Shell, Perl, Python, C++) and AI‑driven automation experience is a plus. Exceptional organizational, problem‑solving, and communication skills. Who You Are Collaborative, diplomatic, and skilled at building consensus. Effective communicator with the ability to align diverse teams. Detail‑oriented and strategic in approach. Passionate about continuous improvement and innovation. Committed to fostering an inclusive and diverse environment. The Team You’ll Be A Part Of You’ll join a multidisciplinary engineering team focused on delivering advanced silicon IP solutions. The team values mentorship, collaboration, and continuous improvement, creating an environment where diverse perspectives drive collective success. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Inclusive work culture supporting diverse backgrounds and experiences. Reasonable accommodations available throughout the recruitment and employment process. For accommodation requests, contact #J-18808-Ljbffr