Tile-Level Place

Tile-Level Place & Route (PnR) - Physical Design Engineer Base pay range: $150,400.00/yr - $225,600.00/yr WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role As a Physical Design Engineer specializing in tile‑level Place and Route (PnR), you will own the implementation and optimization of physical design for high‑performance IP blocks and tiles within complex SoCs. This position demands deep expertise in advanced technology nodes, timing closure, and power‑performance‑area (PPA) optimization. The Person You are a detail‑oriented engineer with strong problem‑solving skills, hands‑on experience in physical design flows, and the ability to collaborate across global teams. You thrive in fast‑paced environments and have a proven track record of closing large, high‑frequency designs. Key Responsibilities Physical Design Implementation:Perform floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and chip finishing for tile‑level designs. Execute PnR flows from netlist to GDSII using industry‑standard EDA tools (Cadence Innovus, Synopsys ICC2/FC). Timing & Power Analysis:Drive timing closure at block and tile level using STA tools (PrimeTime). Conduct IR‑drop/EM analysis and signal integrity checks. Optimize designs for power, performance, and area (PPA). Low‑Power Design Techniques:Implement advanced low‑power strategies such as multi‑Vt optimization, power gating, clock gating, dynamic voltage/frequency scaling (DVFS), and retention flops. Ensure compliance with power intent specifications (UPF/CPF). Verification & Signoff:Perform physical verification (DRC/LVS) using tools like Calibre. Ensure compliance with design rules and manufacturing constraints. Collaboration:Work closely with RTL, architecture, and SoC integration teams to meet design specifications. Coordinate with FCFP/FCT team for tile closure. Automation & Methodology:Develop and maintain scripts (Tcl, Perl, Python) to automate design flows and improve efficiency. Contribute to methodology improvements for advanced nodes (3nm and below). ECO Handling:Implement ECOs for timing and functional fixes at tile level. Preferred Experience Physical design with strong hands‑on PnR experience. Advanced technology nodes (7nm, 5nm, or below). Tools: Cadence Innovus, Synopsys FC, PrimeTime, Calibre, Redhawk. Strong scripting skills (Tcl, Perl, Python). CPU/GPU/DPU or high‑performance IP design experience. Understanding of computer architecture and SoC design flows. Excellent problem‑solving, communication, and ability to work with geographically distributed teams. Familiarity with chip‑level integration and tile partitioning strategies. Proven track record of closing large designs (>2M instances, >2.5GHz frequency). Academic Credentials Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field. EEO Statement & Benefits AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr