PCIe IP ASIC Design Engineer
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Integrate AMD PCI Express subsystems and deploy IP to SoCs Complete synthesis, timing, lint, and CDC closure Implement test, debug, and clock-related design work Apply UPF-based power-aware design flows and techniques Develop automation and scripting for hands-on flow improvement Requirements:
Digital design experience using RTL and Verilog HDL Experience with synthesis, linting, CDC tools, and equivalence checks Knowledge of UPF or CPF power-aware flows Bachelor's or Master's degree in Electrical or Computer Engineering Strong problem-solving, debugging, and communication skills Apply ASIC design expertise, PCIe integration, RTL quality flows, and power-aware techniques to AMD IP enablement.
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