RTL IP Design Engineer AMD
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Develop block-level RTL IP and subsystem specifications Implement and debug RTL using AI-powered methodologies Analyze regressions, simulations, coverage, lint, timing, and DFT Define verification plans and promote design-for-verification practices Resolve subsystem and SoC integration issues collaboratively Requirements:
Strong CPU and embedded microprocessor architecture understanding Proficiency in Verilog, SystemVerilog, and scripting languages Knowledge of AXI, AHB, and AMBA protocols Experience with ASIC simulation, synthesis, timing, and power flows Bachelor's or Master's degree in a technical discipline Apply RTL design, verification, and hardware architecture expertise to AMD security IP in Markham or Austin.
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