Analog and RF Layout Engineer

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s mostinnovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as theyprovide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days arethe same.

Location This is a hybrid role based in Toronto, Canada.

About The Job You're Considering Capgemini Engineering is seeking a

Senior Analog / RF IC Layout Engineer

to join our growing semiconductor engineering team in the Greater Toronto Area. This is an exciting opportunity for an experienced layout professional who enjoys working on leading-edge mixed-signal and RF integrated circuits in advanced process technologies.

Your Role

Lead the physical layout implementation of complex analog, RF, and mixed-signal integrated circuits from concept through tape-out.

Develop and optimize block-level and full-chip layouts in advanced FinFET process technologies, including 7nm and below.

Collaborate closely with Analog, RF, Digital, Physical Design, Verification, and Process teams to achieve aggressive performance, power, area, and yield targets.

Drive floorplanning, device matching, routing strategies, shielding, and critical signal path optimization for high-speed designs.

Implement layout methodologies that address signal integrity, electromigration, IR drop, thermal effects, reliability, and manufacturability requirements.

Perform layout verification, DRC/LVS closure, parasitic extraction review, and tape-out readiness activities.

Support silicon bring-up and debug efforts by partnering with cross-functional engineering teams.

Participate in technical reviews and contribute to layout methodology improvements and best practices.

Mentor junior engineers and provide technical leadership on complex layout challenges.

Required Qualifications Your Skills and Experience

6+ years of experience in Analog, RF, or Mixed-Signal IC Layout.

Proven experience designing and implementing complex layouts in advanced CMOS and FinFET technologies (7nm and below).

Strong expertise in custom IC layout and physical design methodologies.

Hands‑on experience with industry‑standard EDA tools from:

Cadence

Synopsys

Siemens EDA (Mentor Graphics)

Experience with advanced matching techniques, symmetry requirements, shielding, guard rings, and high‑frequency layout practices.

Knowledge of DRC, LVS, parasitic extraction, and physical verification flows.

Strong understanding of device reliability, electromigration, thermal effects, and manufacturing constraints.

Preferred Experience Experience developing layouts for one or more of the following:

High-speed SerDes and transceivers

PLLs and clock generation circuits

Data converters (ADC/DAC)

RF front-end circuits

CMOS drivers and receivers

High-speed I/O interfaces

Data center and networking silicon

AI/ML accelerator devices

The base compensation range for this role in the posted location is:70,751 - 165,984.

Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.

The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.

These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.

It is not typical for candidates to be hired at or near the top of the posted compensation range.

In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.

Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time employees.

Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave

Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)