Formal Verification Specialist
1 month ago
This position is for a Formal Design Verification Engineer. The successful candidate will use formal verification technologies to perform functional verification of design blocks inside Custom AI IPs.
Key Responsibilities:
- Drive Formal Verification Methodology on multiple components inside Custom AI Inference IP.
- Evaluate various formal verification technologies and flows.
Preferred Skills and Experience:
- Knowledge of property checking languages such as SystemVerilog Assertion (SVA) and understanding of HDL languages such as SystemVerilog or Verilog.
- Familiarity with AMBA protocols such as AHB, APB, and AXI.
- Knowledge of Computer Architecture and familiarity with RISC-V ISA.
- Able to use scripting languages such as Python.
- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
- 3 years of experience with hands-on design verification and 2 years in formal verification.
Remote Work:
No
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