Senior Formal Verification Expert
2 weeks ago
Job Title: Formal Design Verification Engineer
This role involves utilizing formal verification technologies to ensure the functional correctness of custom AI inference IP components. The successful candidate will use formal property verification, sequential equivalence checking, and data path validation to drive the design verification process.
Responsibilities:
- Develop and execute verification plans for multiple components. This includes debugging issues and achieving coverage closure.
- Evaluate various formal verification technologies and flows to improve the design verification methodology.
Requirements:
- Knowledge of property checking languages such as SystemVerilog Assertion (SVA) and HDL languages like SystemVerilog or Verilog.
- Familiarity with AMBA protocols such as AHB, APB, and AXI.
- Understanding of computer architecture and RISC-V ISA.
- Proficiency in scripting languages like Python.
- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
- 3 years of experience in design verification with 2 years in formal verification.
Remote Work: No
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