Digital Verification Engineer
4 weeks ago
Synopsys Canada ULC is seeking a highly motivated engineering student to join our Solutions Group in Mississauga. As a Digital Verification Engineer, you will play a critical role in the product development process, ensuring that our designs comply with protocol standards and system requirements.
Key Responsibilities:- Define and track verification test plans
- Design and write constrained-random SystemVerilog testbenches using a verification methodology such as UVM
- Create and examine functional coverage
- Write SystemVerilog assertions
- Debug RTL and gate-level simulation failures
- Firmware debug
- Bug tracking using software tools such as Jira
- Code coverage analysis
- Experience writing scripts in languages such as Perl, Unix shell, or Python
- Experience with object-oriented programming languages such as C++, Java, or Python
- Familiarity with Verilog or SystemVerilog
- Enrolled in a Computer Engineering or Electrical Engineering program, or similar
Synopsys Canada ULC values diversity and is committed to providing equal opportunities to individuals with disabilities. We will provide reasonable accommodations to applicants throughout the recruitment and employment process. If you require an accommodation, please contact hr-help-canada@synopsys.
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