Senior ASIC Digital Design Engineer

3 weeks ago


Ottawa, Ontario, Canada Synopsys, Inc. Full time
Design the Future of DDR PHY IP

At Synopsys, Inc., we're pushing the boundaries of what's possible in the world of DDR PHY IP. As a Senior ASIC Digital Design Engineer, you'll be part of a global team that's shaping the next generation of high-performance, high-bandwidth, and low-latency products.

**Key Responsibilities:**
  • Contribute to all phases of DDR PHY IP design, from specification to productization.
  • Develop and implement complex technical solutions using synthesizable Verilog and System Verilog design concepts.
  • Collaborate with cross-functional teams to drive design flows, including linting, synthesis, timing investigation, and closure.


**Requirements:**
  • BS/MS in Electrical Engineering with at least 2 years of experience in complex technical development.
  • Experience with front-end design flows, including DFT, power optimization techniques, and cross-domain clocking.


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