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High-Speed Communication Protocol Specialist
2 months ago
We are seeking a highly skilled ASIC Design Engineer to join our R&D Professional team. As a key member of our team, you will be responsible for front-end tasks, including ASIC RTL design and verification, solid Verilog, PERL, TCL, and Python skills, and understanding of static timing analysis and synthesis.
Key Responsibilities- Design and verify ASICs at chip level and/or block level
- Develop and maintain test benches and test cases
- Perform RTL and gate-level SDF-annotated simulations and debug
- Collaborate with application engineers and customers to provide guidance on HBM/DDR PHY front-end related aspects
- Participate in the generation of data books, application notes, and white papers
- BSEE degree with 2 years of related experience, or MSEE with related experience/skills
- Excellent communication and presentation skills
Synopsys, Inc. is a leading provider of electronic design automation (EDA) software and services. Our Silicon IP business is focused on integrating more capabilities into an SoC—faster, to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk.
