High Speed Interface Design Engineer with Advanced FinFET Experience
1 day ago
We are seeking a highly skilled High Speed Interface Design Engineer to join our team at Synopsys. As a member of our design team, you will be responsible for implementing high-speed interface IPs and test-chips from RTL to GDSII.
Your key qualifications should include 10+ years of digital or physical design experience, with a focus on advanced FinFET nodes (TSMC 16 nanometer or below). You should have an intimate understanding of the design cycle from RTL to GDSII, including chip-level design. Additionally, you should possess excellent communication and software skills, as well as the ability to develop timing constraints and design architectures to ensure on-time delivery and meet power and area targets.
You will be working closely with multiple functional groups and the product team to ensure the successful implementation of high-speed interface IPs and test-chips. Your role will involve developing methodology and using scripting skills (Perl, Tcl, Python) to automate CAD processes. You should also have a solid understanding of the challenges inherent in analog/digital interfaces and be able to cope with interrupts.
Requirements for this position include an MSEE and 8+ years of experience or a BSEE and 10+ years of experience. Previous project leadership experience is also preferred. You should have a solid understanding of digital/mixed-signal verification flows and SOC integration challenges.
The salary for this position is estimated to be around $150,000 - $200,000 per year, depending on your level of experience and location. If you are a motivated and experienced design engineer looking for a new challenge, we encourage you to apply.
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