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Senior ASIC Hardware and Firmware Verification Engineer
1 month ago
Transforming Lives with AMD Technology
We are committed to enriching our industry, communities, and the world by building great products that accelerate next-generation computing experiences. Our mission is to push the limits of innovation and solve the world's most important challenges.
The Role: ASIC Hardware and Firmware Co-Verification Engineer
This is a critical position within the Security IP Team (SECIP) responsible for developing and maintaining subsystem verification architecture, testbench, and test methodology for Embedded CPU and subcomponent IPs with AXI/AHB buses and HW accelerators such as Cryptography, Data Compression, DMA, etc.
- Design and develop subsystem verification architectures, testbenches, and test methodologies for Embedded CPU and subcomponent IPs with AXI/AHB buses and HW accelerators.
- Participate in subsystem specification and influence IP micro-architecture development (HW and FW co-design and verification aspect), develop and verify abstracted performance models.
- Develop and execute subsystem and block-level test plans.
- Further develop subsystem and block-level testbenches using UVM randomized test methodology and C-DPI directed test methodology.
Preferred Experience:
- Extensive experience in ASIC FW and HW design and verification.
- Proficient in programming languages C, C++, Assembly, Verilog, System Verilog, and several scripting languages (Make, Perl, Python, etc.).
- Excellent knowledge about standard bus/interface protocols.
- Experience with firmware design on commercial microprocessors.
Academic Credentials:
- Bachelor's or Master's degree in Electrical or Computer Engineering.
Estimated Salary: $120,000 - $180,000 per annum
