Senior Engineer, High-Speed Transceiver Development
6 days ago
Company Overview
At Synopsys, Inc., we are at the forefront of innovation in semiconductor design and development. Our mission is to push the boundaries of what is possible in high-speed data transmission.
Job Description
As a Senior Engineer on our System Architecture Team, you will play a crucial role in developing 32Gbps NRZ and 112Gbps PAM4 serial-link transceivers. Your primary responsibilities will include modelling, design, analysis, and algorithms for the transmitter and receiver mixed signal (analog and digital) front-end. We seek an engineer with theoretical knowledge and practical experience to contribute to our team.
You will work closely with a cross-functional design team of analog and digital designers, and hardware engineers. Your involvement will span all stages of development, including:
- Architecture: definition of architecture and specifications for the transmitter and receiver
- Modelling: design and maintenance of the system level model
- Sign-off: system level simulation of the design performance across multiple protocols and channels
- Silicon: qualification and correlation of performance and algorithms in silicon
- Customers: assisting customers on system level performance and algorithmic issues
Required Skills and Qualifications
We require an MSc or PhD in Electrical or Computer Engineering. Key qualifications include one or more of the following:
- Modelling - experience in Matlab/C/systemVerilog modeling of circuits and systems
- Analog – background in high-speed analog CMOS circuit design
- Digital – experience with DSP
- Hardware – awareness on per-protocol handling of RX and TX adaptation; hands-on experience in measurement of transceiver performance
- Communications theory – equalization, coding, noise/crosstalk filtering
Estimated Salary
$150,000 - $200,000 per annum.
Benefits
As a valued member of our team, you will enjoy a comprehensive benefits package, including health insurance, retirement savings plan, and generous paid time off.
Others
Experience in analyzing link budgets for either NRZ and PAM4 high-speed serial links, familiarity with modelling of SERDES transmitters and receivers in Matlab or similar tool, knowledge of circuit topologies in high-speed Rx/Tx SerDes PHY, understanding of Tx/Rx equalization techniques, knowledge of CDR architectures and CDR loop dynamics, knowledge about common high-speed serial data protocols including PCIe, Ethernet, JESD, and CPRI, experience in lab testing of high-speed serial links.
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