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Senior ASIC Verification Engineer
3 months ago
Play a pivotal role in the development of verification frameworks.
Design and implement System Verilog/UVM-based protocol and traffic generators/checkers, and create comprehensive test plans that align with functional and industry standards.
Qualifications- Master's degree preferred; a Bachelor's degree in Computer Science or Electrical Engineering is mandatory.
- 8+ years of substantial experience in the ASIC verification domain.
- Experience in formulating and executing test plans at the block or sub-chip levels for intricate ASIC designs.
- Proficient in System Verilog and scripting languages, particularly Python.
- Deep understanding of UVM methodology is essential.
- Familiarity with assertions and functional coverage is required.
- Experience with code coverage and formal verification tools; knowledge of emerging verification methodologies is advantageous.
- Excellent communication skills and a strong ability to collaborate within a geographically diverse team.
- Responsible for defining, developing, and executing self-checking tests for complex digital ASICs.
Knowledge of Digital Signal Processing (DSP) and/or Forward Error Correction (FEC) is a plus.