Staff Product Engineer

5 days ago

Markham, Ontario, Canada Synopsys, Inc. Full time
Job Title: Staff Product Engineer

At Synopsys, Inc., we are seeking a highly skilled Staff Product Engineer to join our Solutions IP Design Group. As a key member of our team, you will be responsible for developing advanced analog integrated circuit designs using the best-in-class Synopsys suite of tools.

Key Responsibilities:
  • Collaborate with local and global SERDES teams to develop layout for complex analog mixed-signal designs in the latest technology nodes.
  • Take on top-level block ownership and create highly complex blocks.
  • Develop IP in various technology nodes and foundries for various customers in a fast-paced environment.
  • Lead and manage top-level blocks, coordinating with other layout team members for top-level integration.
  • Design and review layout designs, collaborating with the circuit team for feasibility layout of new products.
  • Optimize layout designs for performance, power, and area, working with R&D experts to perform layout verification and resolve any design-related customer issues.
Requirements:
  • BSEE or MSEE with at least 4 years of direct industry experience.
  • In-depth knowledge of layout of analog and mixed signal CMOS circuits.
  • Proficient with full custom analog layout design tool: Custom Compiler (or equivalent).
  • Prior knowledge and proficiency of schematic driven layout editor tools such as Custom Compiler SDL or Virtuoso XL.
  • Solid working knowledge of DRC, LVS, and ability to debug results from ICV tools.
  • Experience with advanced FinFET nodes is required.
  • Ability to use foundry design rule manuals to debug DRC errors is required.
  • Good written and verbal English skills.
  • Experience with TCL, SKILL, PERL, Python, or other language scripting is a plus.
Preferred Qualifications:
  • Experience with layout design with consideration for reliability (EMIR/DFM).
  • Experience with layout design to optimize for parasitic layout effects (matching/proximity effects).
  • Experience with layout optimization for signal integrity (clock/data routes, differential routing, shielding).
  • Implementation of ESD design constraints, latch-up risk mitigation.
  • Experience with PERC is a plus.

This position is based in Canada. Candidates must have legal work status in Canada and be able to work in-office in a hybrid work model.

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