Expert FPGA Design Engineer Opening
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Key Responsibilities
• Design and implement FPGA logic through SystemVerilog
• Translate specifications into effective FPGA micro-architectures
• Manage designs throughout their lifecycle
• Drive timing closure and analyze Clock Domain Crossings
• Oversee CDC verification and synthesis flow
Requirements:
• 10–15 years of practical experience in FPGA design
• Strong current proficiency in SystemVerilog
• Proven experience in ownership of FPGA designs
• Knowledge of analysis and synchronization strategies
• Experience with scripting languages such as Tcl or Python Join a team that values your FPGA design expertise and contributes to groundbreaking projects.
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