Senior FPGA Engineer Role in Ottawa
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Key Responsibilities
• Design and implement micro-architectures in SystemVerilog
• Analyse Clock Domain Crossings (CDC) and confirm synchronizations
• Own the FPGA synthesis process from setup to timing closure
• Evaluate timing and synthesis reports for effective solutions
• Collaborate to ensure designs meet verification standards
Requirements:
• 10-15 years of FPGA design experience necessary
• Strong familiarity with SystemVerilog and CDC
• Experience in configuring FPGA synthesis tools
• Comprehensive understanding of timing constraints (SDC)
• Full-time, on-site work in Ottawa required Lead with your design acumen and contribute to our innovative team in Ottawa. #J-18808-Ljbffr
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