Digital ASIC Design Engineer

Digital ASIC Design Engineer Join to apply for the Digital ASIC Design Engineer role at Ciena As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital design engineer who will be involved in the design of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a digital design engineer will be to propose innovative solutions, in order to design power and area optimized functional blocks for the Wavelogic family of products. Responsibilities As a digital design engineer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects. You will produce an implementation specification document and have it reviewed by your team, architects, analog designers if applicable. You are accountable for the creation and integration of new and existing RTL and/or C source code, algorithms and functions. You are held responsible for designer testing of your code as well as debugging of your code during simulation and regression verification. You will assist the verification team in determining coverage and provide design assertions and waivers as needed. You are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews. You will be involved in lab validation of the product and its prototype if applicable. You are expected to report on status updates on a regular basis. Must Haves Electrical or computer engineering, or other applicable scientific degree at the BEng/BSc or MEng/MSc level. Experience with digital design synthesis, STA, timing closure and asynchronous clock domain crossing. Proficiency above the intermediate level with use of System Verilog for design. Good understanding of timing/power/area analysis and trade-offs both during RTL coding and layout phases. Ability to methodically debug and solve complex technical problems. A highly motivated self-starter, able to work independently, while being a team player. Excellent organization, written and oral (English) communication skills. Assets Experience with digital silicon design backend process. Experience with digital design for low power. Experience with standards and protocols such as OTN, FlexO, Ethernet at rates above 100G. Experience with using Jira for bug tracking and GIT for source code management and revision tracking. Familiarity with programming languages such as Python, Make, bash, object-oriented programming, C, C++, System C. Pay Range The annual salary range for this position is $109,000 - $174,000 CAD. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Benefits Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. EEO Statement Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. #J-18808-Ljbffr