Digital ASIC/FPGA Designer

4 weeks ago


Ottawa, Canada Infotree Global Solutions Full time

Digital ASIC/FPGA Designer with at least 15 years of experience and a bachelor’s degree in engineering or computer science Top Must Have Skills ASIC RTL Design Clock Domain Crossing (CDC) Analysis RTL Synthesis Experience in front-end ASIC design EDA flows including: Synopsys Design/Fusion Compiler, Synopsys VCS simulation; MBIST, DFT; CDC Lint tools Excellent RTL ASIC/FPGA design skills in Verilog and System Verilog Knowledge of networking standards and wired communications protocols (such as Ethernet) Experience with scripting languages such as Python, Perl and TCL Experience with CLIENT Vivado Design Suite Seniority Level Mid‑Senior level Employment Type Contract Job Function Design Industries Staffing and Recruiting and Biotechnology Research Referrals increase your chances of interviewing at Infotree Global Solutions by 2x #J-18808-Ljbffr



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